1. Field of the Invention
The present invention relates to a technology for reducing the power consumption of an entire semiconductor integrated circuit device by supplying a proper voltage to a power supplied circuit in consideration of the power efficiency of a power supplied from a power supply circuit.
2. Description of the Related Art
In a semiconductor integrated circuit, as a plurality of insulating gate-type field effect transistor (hereinafter, abbreviated as ‘MOSFET’) is provided and the length of a channel and the thickness of a gate oxide film, it is possible to obtain high integration or the improvement in an operation speed by reducing the length of a channel and decreasing the thickness of a gate oxide film. However, since a threshold value decreases and a ratio of a leakage current in the power consumption amount increases, the countermeasures for the problems are required.
The power consumption is lowered by dynamically and variably controlling a voltage value supplied from the power supply circuit depending on the output of a processor or an SOC by a DVS (Dynamic Voltage Scaling) technology in the processor or the SOC (System On Chip) coupled to the semiconductor integrated circuit so as to suppress the leakage current.
It is well-known fact that the threshold value or the leakage current of the MOSFET can be controlled to some degree by adjusting a source-substrate voltage or a source-drain voltage. However, a recent research indicates that the leakage current increases due to a BTBT (Band To Band Tunneling) when the source-substrate voltage is equal to or less than a predetermined voltage (for example, see Patent Document 1).
Patent document 1 discloses the technology that the semiconductor integrated circuit controlled where the source of the MOSFET and the voltage of the substrate are controlled separately includes a monitor circuit constituted by a plurality of the MOSFETs, a leakage current detecting device for detecting the leakage current of the monitor circuit, and a substrate generating device, wherein the substrate voltage value of the semiconductor integrated circuit is varied to the substrate power source value which is a minimum data value detected by the monitor circuit in comparison with data output from the leakage current detecting device.
Patent Document 1: JP-A-2005-197411
Non-patent Document 1: pp207 to 211 of ISLPED'01, “Effectiveness of Reverse Body Bias for Leakage Control Scaled Dual Vt CMOS ICs” written by A. Keshavasrzi and seven others
A source voltage value where the semiconductor integrated circuit’ own power has the minimum value is required of the power supply circuit and is supplied to the semiconductor integrated circuit by the power supply circuit. However, the power may not have the minimum value in consideration of the total power of the semiconductor integrated circuit and the power supply circuit. The reason is that the power efficiency is different depending on the supply voltage and the supply voltage in consideration of the power efficiency (power source conversion efficiency) of the power supply circuit.
The power efficiency is approximately 25 to 50% when a regulator is used in the power supply circuit and the power efficiency is approximately 25 to 99% and very wide very wide when a DC-DC converter is used in the power supply circuit. That is, even if the power consumption of the semiconductor integrated circuit is set to the minimum value, the power supply circuit increases all the more when the power efficiency is low the total power of the semiconductor integrated circuit.
As a miniaturization process progresses, the drain-substrate leak current is more prominent than the source-drain leakage current due to the BTBT phenomenon. Accordingly, the power may not have the minimum value in consideration of the total power of the semiconductor integrated circuit and the power supply circuit even if the substrate voltage is applied so as to minimize the drain current of the semiconductor integrated circuit by the substrate voltage control technology disclosed in Patent Document 1. The reason is that the power efficiency of the power supply circuit (power efficiency to an output power supply voltage value) is different depending on the voltage value of the MOS substrate and the substrate current.